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| MOTOROLA Freescale Semiconductor, Inc. SEMICONDUCTOR APPLICATION NOTE Order this document by AN535/D AN535 Phase Locked Loop Design Fundamentals Prepared by: Garth Nash Applications Engineering ABSTRACT The fundamental design concepts for phase-locked loops implemented with integrated circuits are outlined. The necessary equations required to evaluate the basic loop performance are given in conjunction with a brief design example. The parameters in Figure 1 are defined and will be used throughout the text. i(s) + - e(s) G(s) o(s) Freescale Semiconductor, Inc... INTRODUCTION The purpose of this application note is to provide the electronic system designer with the necessary tools to design and evaluate Phase-Locked Loops (PLL) configured with integrated circuits. The majority of all PLL design problems can be approached using the Laplace Transform technique. Therefore, a brief review of Laplace is included to establish a common reference with the reader. Since the scope of this article is practical in nature all theoretical derivations have been omitted, hoping to simplify and clarify the content. A bibliography is included for those who desire to pursue the theoretical aspect. i(s) e(s) o(s) G(s) H(s) H(s) Phase Input Phase Error Output Phase Product of the Individual Feed Forward Transfer Functions Product of the Individual Feedback Transfer Functions Figure 1. Feedback System Using servo theory, the following relationships can be obtained.2 1 q (s) qe(s) + 1 ) G(s) H(s) i G(s) qo(s) + q (s) 1 ) G(s) H(s) i (1) (2) PARAMETER DEFINITION The Laplace Transform permits the representation of the time response f(t) of a system in the complex domain F(s). This response is twofold in nature in that it contains both transient and steady state solutions. Thus, all operating conditions are considered and evaluated. The Laplace transform is valid only for positive real time linear parameters; thus, its use must be justified for the PLL which includes both linear and nonlinear functions. This justification is presented in Chapter Three of Phase Lock Techniques by Gardner.1 These parameters relate to the functions of a PLL as shown in Figure 2. i(s) fi Phase Detector e(s) Filter VCO/VCM o(s) fo fo N o(s)/N Programmable Counter (/N) Figure 2. Phase Locked Loop REV 0 (c) Motorola, Inc. 1994 For More Information On This Product, Go to: www.freescale.com AN535 Freescale Semiconductor, Inc. ERROR CONSTANTS Various inputs can be applied to a system. Typically, these include step position, velocity, and acceleration. The response of type 1, 2, and 3 systems will be examined with the various inputs. e(s) represents the phase error that exists in the phase detector between the incoming reference signal i(s) and the feedback o(s)/N. In evaluating a system, e(s) must be examined in order to determine if the steady state and transient characteristics are optimum and/or satisfactory. The transient response is a function of loop stability and is covered in the next section. The steady state evaluation can be simplified with the use of the final value theorem associated with Laplace. This theorem permits finding the steady state system error e(s) resulting from the input i(s) without transforming back to the time domain.3 Simply stated Lim [(t)] = Lim [se(s)] tR so Where 1 qe(s) + q (s) 1 ) G(s) H(s) i ( 11 ) ( 10 ) The phase detector produces a voltage proportional to the phase difference between the signals i and o/N. This voltage upon filtering is used as the control signal for the VCO/VCM (VCM - Voltage Controlled Multivibrator). Since the VCO/VCM produces a frequency proportional to its input voltage, any time variant signal appearing on the control signal will frequency modulate the VCO/VCM. The output frequency is fo = N fi (3) during phase lock. The phase detector, filter, and VCO/VCM compose the feed forward path with the feedback path containing the programmable divider. Removal of the programmable counter produces unity gain in the feedback path (N = 1). As a result, the output frequency is then equal to that of the input. Freescale Semiconductor, Inc... Various types and orders of loops can be constructed depending upon the configuration of the overall loop transfer function. Identification and examples of these loops are contained in the following two sections. TYPE -- ORDER These two terms are used somewhat indiscriminately in published literature, and to date there has not been an established standard. However, the most common usage will be identified and used in this article. The type of a system refers to the number of poles of the loop transfer function G(s) H(s) located at the origin. Example: let G(s) H(s) + 10 s(s ) 10) (4) The input signal i(s) is characterized as follows: Step position: i(t) = Cp t 0 ( 12 ) This is a type one system since there is only one pole at the origin. The order of a system refers to the highest degree of the polynomial expression 1 + G(s) H(s) = 0 C.E. C Or, in Laplace notation: qi(s) + sp ( 13 ) where Cp is the magnitude of the phase step in radians. This corresponds to shifting the phase of the incoming reference signal by Cp radians: Step velocity: i(t) = Cvt t 0 ( 14 ) (5) which is termed the Characteristic Equation (C.E.). The roots of the characteristic equation become the closed loop poles of the overall transfer function. Example: G(s) H(s) + then 1 ) G(s) H(s) + 1 ) therefore C.E. = s(s +10) +10 C.E. = s2 + 10s + 10 (8) (9) 10 +0 s(s ) 10) (7) 10 s(s ) 10) (6) Or, in Laplace notation: qi(s) + Cv ( 15 ) s2 where Cv is the magnitude of the rate of change of phase in radians per second. This corresponds to inputting a frequency that is different than the feedback portion of the VCO frequency. Thus, Cv is the frequency difference in radians per second seen at the phase detector. Step acceleration: i(t) = Cat2 t 0 Or, in Laplace notation: qi(s) + 2 Ca s3 ( 16 ) ( 17 ) Ca is the magnitude of the frequency rate of change in radians per second per second. This is characterized by a time variant frequency input. Typical loop G(s) H(s) transfer functions for types 1, 2, and 3 are: Type 1 G(s) H(s) + K s(s ) a) ( 18 ) which is a second order polynomial. Thus, for the given G(s) H(s), we obtain a type 1 second order system. 2 MOTOROLA SEMICONDUCTOR For More Information On This Product, APPLICATION INFORMATION Go to: www.freescale.com Freescale Semiconductor, Inc. Type 2 G(s) H(s) + G(s) H(s) + K(s ) a) s2 K(s ) a)(s ) b) s3 ( 19 ) AN535 Type 3 ( 20 ) The final value of the phase error for a type 1 system with a step phase input is found by using Equations 11 and 13. illustrates how the closed loop poles (roots of the characteristic equation) vary with loop gain. For stability, all poles must lie in the left half of the s-plane. The relationship of the system poles and zeroes then determine the degree of stability. The root locus contour can be determined by using the following guidelines.2 Rule 1 - The root locus begins at the poles of G(s) H(s) (K = 0) and ends at the zeroes of G(s) H(s) (K = ), where K is loop gain. Rule 2 - The number of root loci branches is equal to the number of poles or number of zeroes, whichever is greater. The number of zeroes at infinity is the difference between the number of finite poles and finite zeroes of G(s) H(s). Rule 3 - The root locus contour is bounded by asymptotes whose angular position is given by: qe(s) + 1 K 1 ) s(s)a) (s ) a)Cp (s2 ) as ) K) Cp s + ( 21 ) Freescale Semiconductor, Inc... s)a qe(t + R) + Lim s Cp + 0 s2 ) as ) K so ( 22 ) (2n ) 1) p; n + 0, 1, 2, ... #P * #Z ( 23 ) Where #P (#Z) is the number of poles (zeroes). Thus, the final value of the phase error is zero when a step position (phase) is applied. Similarly, applying the three inputs into type 1, 2, and 3 systems and utilizing the final value theorem, the following table can be constructed showing the respective steady state phase errors. Table 1. Steady State Phase Errors for Various System Types Type 1 Step Position Step Velocity Step Acceleration Zero Constant Continually Increasing Type 2 Zero Zero Constant Type 3 Zero Zero Zero Rule 4 - The intersection of the asymptotes is positioned at the center of gravity C.G.: C.G. + SP * SZ #P * #Z ( 24 ) Where P (Z) denotes the summation of the poles (zeroes). Rule 5 - On a given section of the real axis, root loci may be found in the section only if the #P + #Z to the right is odd. Rule 6 - Breakaway points from negative real axis is given by: dK + 0 ds ( 25 ) A zero phase error identifies phase coherence between the two input signals at the phase detector. A constant phase error identifies a phase differential between the two input signals at the phase detector. The magnitude of this differential phase error is proportional to the loop gain and the magnitude of the input step. A continually increasing phase error identifies a time rate change of phase. This is an unlocked condition for the phase loop. Using Table 1, the system type can be determined for specific inputs. For instance, if it is desired for a PLL to track a reference frequency (step velocity) with zero phase error, a minimum of type 2 is required. Again, where K is the loop gain variable factored from the characteristic equation. Example: The root locus for a typical loop transfer function is found as follows: G(s) H(s) + K s(s ) 4) ( 26 ) The root locus has two branches (Rule 2) which begin at s = 0 and s = -4 and ends at the two zeroes located at infinity (Rule 1). The asymptotes can be found according to Rule 3. Since there are two poles and no zeroes, the equation becomes: 2n ) 1 p + 2 p for n + 0 2 3p for n + 1 2 STABILITY The root locus technique of determining the position of system poles and zeroes in the s-plane is often used to graphically visualize the system stability. The graph or plot ( 27 ) MOTOROLA SEMICONDUCTOR APPLICATION INFORMATIONOn This Product, For More Information 3 Go to: www.freescale.com AN535 Freescale Semiconductor, Inc. (* 4 * 0) * (0) 2*0 The response of this type 1, second order system to a step input, is shown in Figure 4. These curves represent the phase response to a step position (phase) input for various damping ratios. The output frequency response as a function of time to a step velocity (frequency) input is also characterized by the same set of figures. The position of the intersection according to the Rule 4 is: s + SP * SZ + #P * #Z ( 28 ) s + -2 The breakaway point, as defined by Rule 6, can be found by first writing the characteristic equation. C.E. + 1 ) G(s) H(s) + 0 +1) K + s2 ) 4s ) K + 0 s(s ) 4) ( 29 ) 1.9 1.8 1.7 1.6 1.5 o (t), NORMALIZED OUTPUT RESPONSE 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 nt 11 12 13 1.5 2.0 1.0 = 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 Now solving for K yields K = -s2 -4s ( 30 ) Freescale Semiconductor, Inc... Taking the derivative with respect to s and setting it equal to zero, then determines the breakaway point. dK + d (* s2 * 4s) ds ds dK + * 2s * 4 + 0 ds or s = -2 ( 33 ) ( 31 ) ( 32 ) is the point of departure. Using this information, the root locus can be plotted as in Figure 3. The second order characteristic equation, given by Equation 29, has be normalized to a standard form2 s2 + 2ns + 2n ( 34 ) Figure 4. Type 1 Second Order Step Response The overshoot and stability as a function of the damping ratio is illustrated by the various plots. Each response is plotted as a function of the normalized time nt. For a given and a lock-up time t, the n required to achieve the desired results can be determined. Example: Assume -2 K=0 where the damping ratio = COS (0 90) and n is the natural frequency as shown in Figure 3. K1 ASYMPTOTE = /2 n CENTER OF GRAVITY K=0 -4 BREAKAWAY POINT j = 0.5 error < 10% for t > 1ms From = 0.5 curve error is less than 10% of final value for all time greater than nt = 4.5. The required n can then be found by: nt = 4.5 ( 35 ) ASYMPTOTE = 3/2 K1 or wn + 4.5 + 4.5 + 4.5krad s t 0.001 ( 36 ) Figure 3. Type 1 Second Order Root Locus Contour 4 MOTOROLA SEMICONDUCTOR For More Information On This Product, APPLICATION INFORMATION Go to: www.freescale.com Freescale Semiconductor, Inc. is typically selected between 0.5 and 1 to yield optimum overshoot and noise performance. Example: Another common loop transfer function takes the form: G(s) H(s) + ( 37 ) o (t), NORMALIZED OUTPUT FREQUENCY 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 s plane 0.2 0.1 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 nt 0.8 1.0 2.0 = 0.1 0.2 0.3 0.4 0.5 0.6 0.7 AN535 (s ) a)k s2 Freescale Semiconductor, Inc... This is a type 2 second order system. A zero is added to provide stability. (Without the zero, the poles would move along the j axis as a function of gain and the system would at all times be oscillatory in nature.) The root locus shown in Figure 5 has two branches beginning at the origin with one asymptote located at 180 degrees. The center of gravity is s = a; however, with only one asymptote, there is no intersection at this point. The root locus lies on a circle centered at s = -a and continues on all portions of the negative real axis to left of the zero. The breakaway point is s = -2a. j K inc n 11 12 13 14 KO1 -2a -a K=0 Figure 6. Type 2 Second Order Step Response these design constraints is now illustrated. It is desired for the system to have the following specifications: Output Frequency 2.0MHz to 3.0MHz 100KHz -- 1ms <20% Figure 5. Type 2 Second Order Root Locus Contour The respective phase or output frequency response of this type 2 second order system to a step position (phase) or velocity (frequency) input is shown in Figure 6. As illustrated in the previous example, the required n can be determined by the use of the graph when and the lock-up time are given. Frequency Steps Phase Coherent Frequency Output Lock-Up Time Between Channels Overshoot NOTE: These specifications characterize a system function similar to a variable time base generator or a frequency synthesizer BANDWIDTH The -3dB bandwidth of the PLL is given by: w * 3dB + wn 1 * 2z2 ) 2 * 4z2 ) 4z4 for a type 1 second order4 system, and by: w-3dB + wn 1 ) 2z2 ) 2 ) 4z2 ) 4z4 for a type 2 second order1 system. 12 12 From the given specifications, the circuit parameters shown in Figure 7 can now be determined. ( 38 ) The devices used to configure the PLL are: Frequency-Phase Detector Voltage Controlled Multivibrator (VCM) MC4044/4344 MC4024/4324 MC4016/4316 ( 39 ) Programmable Counter The forward and feedback transfer functions are given by: G(s) = Kp Kf Ko where Kn = 1/N H(s) = Kn ( 40 ) ( 41 ) PHASE-LOCKED LOOP DESIGN EXAMPLE The design of a PLL typically involves determining the type of loop required, selecting the proper bandwidth, and establishing the desired stability. A fundamental approach to The programmable counter divide ratio Kn can be found from Equation 3. MOTOROLA SEMICONDUCTOR APPLICATION INFORMATIONOn This Product, For More Information 5 Go to: www.freescale.com AN535 fi Freescale Semiconductor, Inc. Phase Detector Kp Filter Kf VCM Ko fo Programmable Counter Kn Figure 7. Phase-Locked Loop Circuit Parameters f min f min N min + o +o + 2MHz + 20 100KHz fi fstep f max + 3MHz + 30 N max + o 100KHz fstep ( 42 ) Where Kv is the sensitivity in radians per second per volt. From the curve in Figure 8, Kv is found by taking the reciprocal of the slope. Kv + 4MHz * 1.5MHz 2p rad s V 5V * 3.6V Kv = 11.2 x 106 rad/s/V ( 46 ) ( 43 ) Freescale Semiconductor, Inc... Kn + 1 to 1 20 30 ( 44 ) Thus x10 Ko + 11.2s 6 rad s V ( 47 ) A type 2 system is required to produce a phase coherent output relative to the input (See Table 1). The root locus contour is shown in Figure 5 and the system step response is illustrated by Figure 6. The operating range of the MC4024/4324 VCM must cover 2MHz to 3MHz. Selecting the VCM control capacitor according to the rules contained on the data sheet yields C = 100pF. The desired operating range is then centered within the total range of the device. The input voltage versus output frequency is shown in Figure 8. 5.5 5.0 The s in the denominator converts the frequency characteristics of the VCM to phase, i.e., phase is the integral of frequency. The gain constant for the MC4044/4344 phase detector is found by5 DFHigh * UFLow + 2.3V * 0.9V + 0.111V rad 4p 2(2p) ( 48 ) Since a type 2 system is required (phase coherent output) the loop transfer function must take the form of Equation 19. The parameters thus far determined include Kp, Ko, Kn leaving only Kf as the variable for design. Writing the loop transfer function and relating it to Equation 19 Kp + G(s)H(s) + Kp Kv K n Kf s + K(s ) a) s2 ( 49 ) VCC = 5.0 Vdc +125C -55C +25C V in , INPUT VOLTAGE (VOLTS) 4.0 -55C +125C +25C 3.0 Thus, Kf must take the form Kf + s ) a s ( 50 ) 2.0 1.0 in order to provide all of the necessary poles and zeroes for the required G(s) H(s). The circuit shown in Figure 9 yields the desired results. 0 1.0 2.0 3.0 4.0 5.0 6.0 fout, OUTPUT FREQUENCY (MHz) R2 R1 A C 0 Figure 8. MC4324 Input Voltage versus Output Frequency (100pF Feedback Capacitor) The transfer function of the VCM is given by: K Ko + sv ( 45 ) Figure 9. Active Filter Design 6 MOTOROLA SEMICONDUCTOR For More Information On This Product, APPLICATION INFORMATION Go to: www.freescale.com Freescale Semiconductor, Inc. Kf is expressed by R Cs ) 1 for largeA Kf + 2 R1Cs where A is voltage gain of the amplifier. R1, R2, and C are then the variables used to establish the overall loop characteristics. The MC4044/4344 provides the active circuitry required to configure the filter Kf. An additional low current high buffering device or FET can be used to boost the input impedance, thus minimizing the leakage current from the capacitor C between sample updates. As a result, longer sample periods are achievable. Since the gain of the active filter circuitry in the MC4044/4344 is not infinite, a gain correction factor Kc must be applied to Kf in order to properly characterize the function. Kc is found experimentally to be Kc = 0.5. Kfc + Kf Kc + 0.5 R2Cs ) 1 R1Cs ( 52 ) wn + 4.5 + 4.5 + 4.5krad s t 0.001 Rewriting Equation 57 0.5 Kp Kv wn2N ( 51 ) 0.5 Kp Kv R1CN + wn2 AN535 ( 57 ) and 0.5 Kp Kv R2 R1N + 2zwn ( 58 ) With the use of an active filter whose open loop gain (A) is large (Kc = 1), Equations 57 and 58 become Kp Kv R1CN + wn2 ( 59 ) Kp Kv R 2 R1N + 2zwn ( 60 ) Freescale Semiconductor, Inc... The percent overshoot and settling time are now used to determine n. From Figure 6, it is seen that a damping ratio = 0.8 will produce a peak overshoot less than 20% and will settle within 5% at nt = 4.5. The required lock-up time is 1ms. (For large gain, Equation 51 applies.) The PLL circuit diagram is shown in Figure 11 and its Laplace representation in Figure 10. The loop transfer function is G(s) H(s) = Kp Kfc Ko Kn G(s)H(s) + Kp(0.5) R2Cs ) 1 R1Cs Kv s 1 N ( 53 ) ( 54 ) ( 61 ) R1C + ( 62 ) The characteristic equation takes the form C.E. + 1 ) G(s) H(s) + 0 + s2 ) 0.5 Kp Kv R2 R1N s) 0.5 Kp Kv R1CN + (0.5) (0.111) (11.2 x 106) (4500)2 (30) R1C = 0.00102 ( 55 ) (Maximum overshoot occurs at Nmax which is minimum loop gain) Let Then ( 56 ) Use R1 = 2k C = 0.5F R1 + 0.00102 + 2.04kW 0.5 x 10-6 Relating Equation 55 to the standard form given by Equation 34 s2 ) 0.5 Kp Kv R2 R1N s) 0.5 Kp Kv R1CN = s2 + 2ns + n2 Equating like coefficients yields i(s) + Kp = 0.111V/rad - R Cs ) 1 Kf + 2 2R1Cs Ko + 11.2 * 106 rad s V s o(s) Kn + 1 to 1 30 20 Figure 10. Laplace Representation of Diagram in Figure 11. MOTOROLA SEMICONDUCTOR APPLICATION INFORMATIONOn This Product, For More Information 7 Go to: www.freescale.com AN535 Freescale Semiconductor, Inc. VCC VCC 1k fi 1 13 4 5 *R1 (2k) *R1 (2k) *MPS6571 MC4344 * Denotes parts external to the MC4344 + + 9 8 2 *C (0.5) *R2 (680) 3 MC4324 C = 100pF 3 2 11 10 4 6 fo Freescale Semiconductor, Inc... 13 12 5 10 MC4316 11 14 3 4 6 3 12 1 5 10 MC4316 11 14 4 6 2 2 P0 P1 P2 P3 P0 P1 P2 P3 Figure 11. Circuit Diagram of Type 2 Phase-Locked Loop R1 is typically selected greater than 1k. Solving for R2 in Equation 58 2z wn R1N 2z R2 + + Kp Kv (0.5) C wn 2(0.8) (0.5 x 10-6)(4.5k) -2.94k ( 63 ) N = 20 n = 5.64krad/s = 0.961 N = 30 n = 4.61krad/s = 0.785 + = 711 Use R2 = 680 All circuit parameters have now been determined and the PLL can be properly configured. Since the loop gain is a function of the divide ratio Kn, the closed loop poles will vary its position as Kn varies. The root locus shown in Figure 12 illustrates the closed loop pole variation. The loop was designed for the programmable counter N = 30. The system response for N = 20 exhibits a wider bandwidth and larger damping factor, thus reducing both lock-up time and percent overshoot (see Figure 14). Figure 12. Root Locus Variation NOTE: The type 2 second order loop was illustrated as a design sample because it provides excellent performance for both type 1 and 2 applications. Even in systems that do not require phase coherency, a type 2 loop still offers an optimum design. 8 MOTOROLA SEMICONDUCTOR For More Information On This Product, APPLICATION INFORMATION Go to: www.freescale.com Freescale Semiconductor, Inc. EXPERIMENTAL RESULTS Figure 13 shows the theoretical transient frequency response of the previously designed system. The curve N = 30 illustrates the frequency response when the programmable counter is stepped from 29 to 30, thus producing a change in the output frequency from 2.9MHz to 3.0MHz. An overshoot of 18% is obtained and the output frequency is within 5kHz of the final value one millisecond after the applied step. The curve N = 20 illustrates the output frequency change as the programmable counter is stepped from 21 to 20. Since the frequency is proportional to the VCM control voltage, the PLL frequency response can be observed with an oscilloscope by monitoring pin 2 of the VCM. The average frequency response as calculated by the Laplace method is found experimentally by smoothing this voltage at pin 2 with a simple RC filter whose time constant is long compared to the phase detector sampling rate, but short compared to the PLL response time. With the programmable counter set at 29 the quiescent control voltage at pin 2 is approximately 4.37 volts. Upon changing the counter divide ratio to 30, the control voltage increases to 4.43 volts as shown in Figure 14. A similar transient occurs when stepping the programmable counter from 21 to 20. Figure 14 illustrated that the experimental results obtained from the configured system follows the predicted results shown in Figure 13. Linearity is maintained for phase errors less than 2, i.e. there is no cycle slippage at the phase detector. AN535 4.43 V N STEPPED FROM 29 TO 30 4.37 V 3.89 V N STEPPED FROM 21 TO 20 3.83 V V = 0.05 V/cm H = 0.5 ms/cm Figure 14. VCM Control Voltage (Frequency) Transient Figure 15 is a theoretical plot of the VCM control voltage transient as calculated by a computer program. The computer program is written with the parameters of Equations 58 and 59 (type 2) as the input variables and is valid for all damping ratios of 1.0. The program prints or plots control voltage transient versus time for desired settings of the programmable counter. The lock-up time can then be readily determined as the various parameters are varied. (If stepping from a higher divide ratio to a lower one, the transient will be negative.) Figures 14 and 15 also exhibit a close correlation between experimental and analytical results. Freescale Semiconductor, Inc... N = 30 OUTPUT FREQUENCY (MHz) 3.0 N STEPPED FROM 29 TO 30 2.9 Step Input 2.1 N STEPPED FROM 21 TO 20 2.0 N = 20 0 0.5 1.0 TIME (ms) 1.5 2.0 SUMMARY This application note describes the basic control system techniques required for phase-locked loop design. Criteria for the selection of the optimum type of loop and methods for establishing the desired performance characteristics are presented. A design example is illustrated in a step-by-step approach along with the comparison of the experimental and analytical results. Figure 13. Frequency-Time Response MOTOROLA SEMICONDUCTOR APPLICATION INFORMATIONOn This Product, For More Information 9 Go to: www.freescale.com AN535 Freescale Semiconductor, Inc. *THE PARAMETERS LISTED BELOW APPLY TO THE FOLLOWING PLOT PHASE DETECTOR GAIN CONSTANT VCM GAIN CONSTANT FILTER INPUT RESISTOR FILTER FEEDBACK RESISTOR FILTER CAPACITOR DIVIDER VALUE REFERENCE FREQUENCY OUTPUT FREQUENCY CHANGE P1 = 0.111 VOLTS PER RADIAN V1 =1.12 E+7 RAD PER VOLT R1 = 3900 OHMS (R1C = 2k) R2 = 680 OHMS C1 = 0.5 MICROFARADS N1-N2 = 29 - 30 F1 = 100000 CPS F5 = 100000 CPS P2 = 0.111 V2 = 1.12 E+7 R3 = 3900 (R1C = 2k) R4 = 680 C2 = 0.5 N3-N4 = 21 - 20 F2 (F6) = 100000 (100000) Freescale Semiconductor, Inc... PLOT OF FUNCTIONS (NOTE: Y(T) IS `+', Z(T) IS `*', AND `O' IS COMMON) FOR T: FOR FCTS: TOP = 0 LEFT = 0 BOTTOM = 0.0015 RIGHT = 0.12 INCREMENT = 0.0005 INCREMENT = 0.002 Figure 15. VCM Control Signal Transient 10 MOTOROLA SEMICONDUCTOR For More Information On This Product, APPLICATION INFORMATION Go to: www.freescale.com Freescale Semiconductor, Inc. Bibliography 1. Topic: Type Two System Analysis Gardner, F. M., Phase Lock Techniques, Wiley, New York, Second Edition, 1967 2. Topic: Root Locus Techniques Kuo, B. C., Automatic Control Systems, Prentice-Hall, Inc., New Jersey, 1962 3. Topic: Laplace Techniques McCollum, P. and Brown, B., Laplace Transform Tables and Theorems, Holt, New York, 1965 4. Topic: Type One System Analysis Truxal, J. G., Automatic Feedback Control System Synthesis, McGraw-Hill, New York, 1955 5. Topic: Phase Detector Gain Constant DeLaune, Jon, MTTL and MECL Avionics Digital Frequency Synthesizer, AN532 AN535 Freescale Semiconductor, Inc... MOTOROLA SEMICONDUCTOR APPLICATION INFORMATIONOn This Product, For More Information 11 Go to: www.freescale.com AN535 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan. ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 12 AN535/D MOTOROLA SEMICONDUCTOR For More Information On This Product, APPLICATION INFORMATION Go to: www.freescale.com |
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